Generally the invention relates to vertical bipolar transistors, and more specifically to high-speed bipolar transistors having an SiGe (silicon-germanium) heterojunction base.
In one embodiment, a method of making a compact, high-speed bipolar transistor of low complexity, having a low collector-substrate capacitance and a low capacitance between the extrinsic base and the collector is described.
Consequently, the bipolar transistor includes an intrinsic collector semiconductor region surrounded by a lateral isolation region; a semiconductor layer, includes for example a SiGe heterojunction, situated partially between the emitter and the intrinsic collector and extending on either side of the emitter above the lateral isolation region. The bipolar transistor includes an intrinsic base region formed in said semiconductor layer between the emitter and the intrinsic collector. It also includes an extrinsic base region and an extrinsic collector region including respectively first zones formed in said semiconductor layer. These first zones are situated respectively on either side of the emitter and above a first part of the lateral isolation region and are mutually isolated electrically by a second part of the lateral isolation region. The extrinsic base and extrinsic collector regions also includes second zones extending into the intrinsic collector, in practice produced by implantation. Finally, base and collector metallizations are respectively situated in contact with said first corresponding zones above said first part of the lateral isolation region.
In other words, the bipolar transistor according to the invention does not have an extrinsic collector formed from a collector well and from a buried layer. Here, the extrinsic collector is formed mainly in the semiconductor layer, for example with a heterojunction. The base, and consequently the base metallization, does not completely surround the emitter. As a result, the extrinsic collector and extrinsic base regions need to be isolated electrically, may be achieved by a part of the lateral isolation region.
The bipolar transistor therefore has not only a base metallization protruding into the field oxide, but also an extrinsic collector metallization protruding into the field oxide, which contributes to further increasing the operating speed of the transistor and which makes it possible to obtain both a low extrinsic base-collector capacitance and also a low collector-substrate capacitance.
Furthermore, the absence of an offset collector well makes it possible to obtain a particularly compact bipolar transistor.
According to one embodiment, the transistor includes two layers of amorphous silicon lying on the first part of the lateral isolation region, under said first zones of the extrinsic base and of the extrinsic collector, respectively, these two amorphous silicon layers protruding respectively beyond the lateral isolation region in the direction of the emitter.
The presence of these amorphous silicon layers makes it possible, during selective epitaxy which is one of the characteristics of the fabrication process, to obtain a growth rate which is approximately the same for the polycrystalline silicon of the semiconductor layer, growing above the field oxide zone, and for the single-crystal silicon of this semiconductor layer growing over the silicon region of the intrinsic collector.
According to one embodiment of the, the emitter region includes a projecting zone surrounded by isolating spacers and extending into a narrower window in contact with the intrinsic base. The distance between the edge of the window and the isolating spacer situated on the intrinsic collector side is thus advantageously greater than the distance between the edge of the window and the isolating spacer situated on the extrinsic base side. This makes it possible to avoid, during n+implantation, for example of the intrinsic collector, having a protrusion of this implanted zone into the window of the emitter.
In one embodiment a process for fabricating a vertical bipolar transistor is described. The process includes implanting an intrinsic collector region into a semiconductor substrate zone surrounded by a lateral isolation region and producing extrinsic base, intrinsic base and extrinsic collector regions. This production step includes the formation, by selective epitaxy, of a semiconductor layer, for example with a SiGe heterojunction layer, extending over the intrinsic collector region and above the lateral isolation region. This production step also includes implantations of dopants through the first predetermined zones of this semiconductor layer, for example this heterojunction layer, said zones being situated respectively on either side of the intrinsic collector and above a first part of the lateral isolation region and being mutually isolated electrically by a second part of the lateral isolation region. Implantations are also provided in second predetermined zones of the intrinsic collector. In this way, the extrinsic base and extrinsic collector regions are formed. The process also includes a step of producing the contact metallizations including the production of the base and collector contact metallizations respectively on either side of the emitter region and above the first part of the lateral isolation region.
It should be noted here that the production of the collector, by implantation, and not by epitaxy, contributes to reducing the complexity, and consequently the cost, of producing the transistor.
According to one method of implementing the process, the formation of the semiconductor layer, for example the heterojunction layer, includes the deposition of an amorphous silicon layer on the intrinsic collector and on the lateral isolation region; the etching of this amorphous silicon layer so as to leave, on each side of the exposed surface of the intrinsic collector, two distinct amorphous silicon zones extending respectively over the first part of the lateral isolation region and protruding respectively over the exposed surface of the intrinsic collector, followed by said selective epitaxy on the exposed zone of the intrinsic collector and on the two distinct amorphous silicon zones.
The process furthermore includes advantageously producing the emitter region, by depositing an insulating bilayer on the semiconductor layer, for example the heterojunction layer, then etching of the bilayer so as to produce a window exposing a zone of the semiconductor layer situated above the intrinsic collector. This process also includes the deposition of a polysilicon layer on the unetched part of the insulating bilayer and in said window, then the etching of the polysilicon so as to make a protecting polysilicon part which is wider than the window, the distance between the edge of the window and the edge of the projecting part on the extrinsic collector side being larger than the distance between the edge of the window and the edge of the projecting part on the extrinsic base side.